1. Introduction
This invention relates to methods for the manufacture of circuit boards and to the boards produced thereby. More particularly, this invention relates to a method for making multilayer circuit boards by sequential formation of layers having signal layers separated from each other by interconnect layers.
2. Description of Related Art
Multilayer circuits enable formation of multiple circuits in minimal volume. They typically comprise a stack of layers with layers of signal lines (conductors) separated from each other by dielectric layers having plated holes known as "buried vias" providing electrical interconnections between the layers.
Current methods for fabricating multilayer boards are extensions of methods used for fabricating double-sided boards. A typical method comprises fabrication of separate innerlayers having circuit patterns disposed over their surface. A photosensitive material is coated over the copper surfaces of a copper clad innerlayer material, imaged, developed and etched to form a conductor pattern in the copper cladding protected by the photosensitive coating. After etching, the photosensitive coating is stripped from the copper leaving the circuit pattern on the surface of the base material. Following formation of the innerlayers, a multilayer stack is formed by preparing a lay up of innerlayers, ground plane layers, power plane layers, etc., typically separated from each other by a dielectric prepreg (a layer consisting of glass cloth impregnated with partially cured material, typically a B-stage epoxy resin). The outer layers of the stack comprise copper clad glass filled epoxy board material with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin.
Interconnections or through-holes, buried vias and blind hole interconnections are used to connect circuit layers within a multilayer board. The buried vias are plated through holes connecting two sides of an innerlayer. Blind vias typically pass through one surface of the stack and pass into and stop within the stack. Regardless of the form of interconnection, holes are generally drilled at appropriate locations through the stack, catalyzed by contact with a plating catalyst and metallized, typically with electroless copper overplated with electrolytic copper, to provide electrical contact between circuit innerlayers.
The uses, advantages and fabrication techniques for the manufacture of multilayer boards are described by Coombs, Printed Circuits Handbook, McGraw Hill Book Company, New York, 2nd edition, pp. 20-3 to 23-19, 1979, incorporated herein by reference.
Multilayer boards have become increasingly complex. For example, boards for main frame computers may have as many as 36 layers of circuitry, with the complete stack having a thickness of about 1/4 inch. These boards are typically designed with 4 mil wide signal lines and 12 mil diameter vias for interconnections between signal line layers. For higher performance, higher speed, higher circuit density and higher surface impedance, it is desired to reduce signal lines to a width of 2 mils or less and vias to a diameter of 2 to 5 mils or less. In order to maintain characteristic impedance of 50 ohms and low levels of cross-talk, the thickness of the dielectric is normally less than 1 mil.
In addition to decreasing line width and via diameter, it is desired to avoid manufacturing problems associated with multilayer board fabrication. Current manufacturing methods utilize innerlayer materials comprising glass reinforced resin of about 4 to 5 mils in thickness clad with copper on both surfaces, glass/epoxy multilayer boards and ceramic co-fired boards. Since lamination is at a temperature above 150.degree. C., the laminate shrinks during cooling to the extent permitted by the copper cladding. If the copper is etched to form a discontinuous pattern, laminate shrinkage may not be restrained by copper cladding. Consequently, further shrinkage may occur. This shrinkage may have an adverse effect on dimensional stability and layer registration.
The lamination procedure for formation of a multilayer stack includes a lay up of components prior to lamination. Care must be exercised to avoid shifting of innerlayers during lamination. Otherwise, the layers will not be aligned and electrical contact between layers will not be achieved. In addition, during lay up, air is often trapped in spaces adjacent to signal lines because a solid pre-preg is laid over the signal lines that does not fill recesses between signal lines. Care should be taken to evacuate entrapped air. Residual air pockets can cause defects and subsequent problems during use of the multilayer board.